25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems – DDECS 2022

April 6 – 8, 2022
Prague | Czech Republic

Conference Program PDF VERSION »

On-line access

There will be a possibility of a free access to the conference presentations. In case you are interested, feel free to ask for the link to Zoom by sending your request to Rudolf Kinc.

Program Overview

Wednesday, April 6

Start Time Session Presenters Title Chair
8:30 Registration
9:00 Opening Session
9:30 Keynote 1 Janusz Rajski / Siemens A New Role of Design for Test in Silicon Lifecycle Management Hana Kubátová
10:15 Industrial Talk 1 Pavel Benáček / Intel Experiences building a P4 Compiler for FPGAs Hana Kubátová
10:45 Short coffee break
11:00 Session 1 RISC Processors Alberto Bosio
12:15 Lunch break
13:15 Embedded Tutorial Lukáš Sekanina / VUT Brno Hardware-Aware Neural Architecture Search Maksim Jenihhin
14:15 Session 2 Novel Computing Architectures Maksim Jenihhin
15:20 Poster (Regular) + Coffee
16:20 Session 3 Analog and Mixed-Signal Design Viera Stopjaková
17:40 Free time
18:00 Welcome Reception

Thursday, April 7

Start Time Session Presenters Title Chair
8:30 Registration
9:00 Keynote 2 Rolf Drechsler / University of Bremen Towards Polynomial Formal Verification of Complex Arithmetic Circuits Petr Fišer
9:45 Industrial Talk 2 Tomáš Martinec / Sysgo Safety-critical embedded software technology innovations in Sysgo Petr Fišer
10:15 Short coffee break
10:30 Session 4 Hardware Security Martin Novotný
11:50 Lunch break
13:00 Panel Session Secure hardware architectures and systems Nele Mentens
14:00 Short break
14:15 Special Session Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? Alberto Bosio
15:45 Free time
17:00 Social Event

Friday, April 8

Start Time Session Presenters Title Chair
9:30 Keynote 3 Lejla Batina / Radboud University AI and Side-channel analysis: Lessons learned so far Nele Mentens
10:15 Session 5 Formal Verification Katarína Jelemenská
11:30 Short coffee break
11:45 Session 6 Emerging Technologies and New Computing Paradigms Lukáš Sekanina
13:00 Lunch break
14:00 Session 7 Stochastic Computing Elena-Ioana Vatajelu
14:50 Poster (Informal) + Coffee
15:20 Session 8 Reliability and Resilience of DNNs Giorgio Di Natale
16:10 Closing
16:20 Conference end

Detailed Program

Session 1: RISC Processors

Paper ID Paper Title Authors Organisation(s)
112Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set ExtensionsMilan FUNCK (1) Vladimir HERDT (1,2) Rolf DRECHSLER (1,2)1: DFKI GmbH, Germany; 2: University of Bremen, Germany
114Early Performance Estimation of Embedded Software on RISC-V Processor using Linear RegressionWeiyan ZHANG (1) Mehran GOLI (1,2) Rolf DRECHSLER (1,2)1: DFKI GmbH, Germany; 2: University of Bremen, Germany
116Processor Extensions for Hardware Instruction Replay against Fault Injection AttacksNoura AIT MANSSOUR (1,3) Vianney LAPOTRE (2,3) Guy GOGNIAT (2,3) Arnaud TISSERAND (1,3)1: UBS, Lab-STICC, France; 2: Université Bretagne Sud; 3: CNRS, Lab-STICC, France

Session 2: Novel Computing Architectures

Paper ID Paper Title Authors Organisation(s)
126AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline StagesZaheer TABASSAM (1) Syed Rameez NAQVI (2) Andreas STEININGER (1)1: TU Wien, Austria; 2: CUI, Wah Campus, Pakistan
149A Design Space Exploration Framework for Memristor-Based Crossbar ArchitectureMario BARBARESCHI (1) Alberto BOSIO (2) Ian O'CONNOR (2) Petr FIŠER (3) Marcello TRAIOLA (4)1: Department of Electrical Engineering and Information Technology, University of Naples Federico II, Naples, Italy; 2: Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully, France; 3: Czech Technical University in Prague, Czech Republic; 4: University of Rennes, Inria, CNRS, IRISA, UMR6074
134/SArithsGen: Arithmetic Circuit Generator for Hardware AcceleratorsJan KLHUFEK Vojtech MRAZEKBrno University of Technology, Czech Republic

Session 3: Analog and Mixed-Signal Design

Paper ID Paper Title Authors Organisation(s)
102Hexapod robotic system for indoor neutron and gamma radiation mapping and inspectionAntonis BANOS Yannick VERBELEN Suresh KALUVAN Chris HUTSON Matthew RYAN TUCKER Tom B. SCOTTUniversity of Bristol, United Kingdom
163Autocalibration Approach for Improving Robustness of Analog ICsDavid MALJAR Daniel ARBET Martin KOVÁČ Róbert ONDICA Viera STOPJAKOVÁSlovak University of Technology, Slovak Republic
119/SA Radiation Tolerant CML Voltage-Controlled Oscillator in 65 nm CMOSJaime Sebastian CARDENAS CHAVEZ (1) Cheng GU (1) Zhi Chao ZHANG (1) Riu CHEN (1) Hormoz DJAHANSHAH (2)1: University of Saskatchewan, Canada; 2: Microchip Technology
162/SOn-Chip Current Sensing Approaches for DC-DC ConvertersRichard RAVASZ Adam HUDEC Daniel ARBET Viera STOPJAKOVÁSlovak University of Technology, Slovak Republic

Session 4: Hardware Security

Paper ID Paper Title Authors Organisation(s)
142Hardware Obfuscation of Digital FIR FiltersLevent AKSOY (1) Alexander HEPP (2) Johanna BAEHR (2) Samuel PAGLIARINI (1)1: Tallinn University of Technology, Estonia; 2: Technical University of Munich, Germany
155Exploiting PUF Variation to Detect Fault Injection AttacksTroya Cagil KOYLU Luiza CAETANO GARAFFA Cezar Rodolfo WEDIG REINBRECHT Mahdi ZAHEDI Said HAMDIOUI Mottaqiallah TAOUILDelft University of Technology, Netherlands, The
139/SVersatile Hardware Framework for Elliptic Curve CryptographyVít MAŠEK Martin NOVOTNÝCzech Technical University in Prague, Czech Republic
141/SCorrelation Power Analysis of SipHashMatúš OLEKŠÁK Vojtěch MIŠKOVSKÝCzech Technical University in Prague, Czech Republic

Session 5: Formal Verification

Paper ID Paper Title Authors Organisation(s)
110Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model CheckingJosef STRNADELBrno University of Technology, Czech Republic
128Functional Verification of Arithmetic Circuits: Survey of Formal MethodsMaciej CIESIELSKI Atif YASIN Jiteshri DASARIUniversity of Massachusetts, Amherst, MA, USA
164On SAT-Based Model Checking of Speed-Independent CircuitsFlorian HUEMER Robert NAJVIRT Andreas STEININGERInstitute for Computer Engineering, TU Wien, Vienna, Austria

Session 6: Emerging Technologies and New Computing Paradigms

Paper ID Paper Title Authors Organisation(s)
140Synaptic Control for Hardware Implementation of Spike Timing Dependent PlasticitySalah DADDINOUNOU Elena-Ioana VATAJELUUniv. Grenoble Alpes, CNRS, Grenoble INP, TIMA, France
125Programmable logic elements using multigate ambipolar transistorsAshton SNELGROVE Pierre-Emmanuel GAILLARDONUniversity of Utah, USA
136A Concept Towards Pressure-Controlled Microfluidic NetworksGerold FINK (1) Medina HAMIDOVIĆ (1) Werner HASELMAYR (1) Robert WILLE (2,3)1: Johannes Kepler University Linz, Austria; 2: Technical University of Munich, Munich, Germany; 3: Software Competence Center Hagenberg GmbH (SCCH), Hagenberg, Austria

Session 7: Stochastic Computing

Paper ID Paper Title Authors Organisation(s)
105Stochastic Computing Architectures for Lightweight LSTM Neural NetworksRoshwin SENGUPTA (1) Ilia POLIAN (1) John P. HAYES (2)1: University of Stuttgart, Germany; 2: University of Michigan; USA
147Analyzing Multilevel Stochastic Circuits using Correlation MatricesOwen S. HOFFEND John P. HAYESUniversity of Michigan, USA

Session 8: Reliability and Resilience of DNNs

Paper ID Paper Title Authors Organisation(s)
150Selective Hardening of Critical Neurons in Deep Neural NetworksAnnachiara RUOSPO (1) Gabriele GAVARINI (1) Ilaria BRAGAGLIA (1) Marcello TRAIOLA (2) Alberto BOSIO (3) Ernesto SANCHEZ (1)1: Politecnico di Torino, Italy; 2: Inria, University of Rennes, CNRS, IRISA, Rennes, France; 3: Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, France
158Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case StudyAlessandro VERONESI (1) Francesco DALL'OCCO (2) Davide BERTOZZI (2) Michele FAVALLI (2) Milos KRSTIC (1,3)1: IHP microelectronics, Germany; 2: University of Ferrara, Italy; 3: Universität Potsdam, Germany

Regular Posters

Paper ID Paper Title Authors Organisation(s)
104Fault Tolerant Synchronous Multi-Channel Buck Converter for Nuclear Inspection InstrumentsVERBELEN, Yannick; BANOS, Antonios; SCOTT, Tom B.University of Bristol, United Kingdom
109Hardware Accelerated FrodoKEM on RISC-VKARL, Patrick (1) FRITZMANN, Tim (1) SIGL, Georg (1,2)1: Technical University of Munich, Germany; 2: Fraunhofer Institute for Applied and Integrated Security, Germany
113Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog FiltersCOŞKUN, Kemal Çağlar1: University of Bremen, Germany; 2: DFKI GmbH, Germany
133ML-based Power Estimation of Convolutional Neural Networks on GPGPUsMETZ, Christopher A. (1) GOLI, Mehran (1,2) DRECHSLER, Rolf (1,2)1: Institute of Computer Science, Universität Bremen, Germany; 2: Cyber-Physical Systems, DFKI Bremen, Germany
137On the optimization of Software Obfuscation against Hardware Trojans in MicroprocessorsCASSANO, Luca (1) LAZZERI, Elia (1) LITOVCHENKO, Nikita (1) DI NATALE, Giorgio (2) 1: Politecnico di Milano, Italy; 2: Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, France

Informal Posters

Paper ID Paper Title Authors Organisation(s)
169Scalable FPGA hardware accelerator for SVM inferenceAFTOWICZ, Marcin (1) LEHNIGER, Kai (1) LANGENDOERFER, Peter (1,2)1: IHP - Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany; 2: BTU CS - Brandenburg University of Technology Cottbus-Senftenberg, Germany
170Identifying Critical Flip-flops in Circuits with Graph Convolutional NetworksLU, Li (1) CHEN, Junchao (1,2) ULBRICHT, Markus (1) KRSTIC, Milos (1,2)1: IHP-Leibniz-Institut für innovative Mikroelektronik, Germany; 2: University of Potsdam, Potsdam, Germany
171Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo SimulationREZNICEK, Jan; KOHLIK, Martin; KUBATOVA, HanaCzech Technical University in Prague, Czech Republic