The technology evolution addresses the demand for faster computers. Despite the achieved speed-up in terms of memory and computation performances, the communication between the memories and the processor remains a bottleneck of today’s computers. The Computation in Memory (CiM) paradigm aims at solving this problem by moving the computation directly inside the memory, eliminating thus the need for data transfer between memory and processor. Among the available CiM implementations, this presentation will focus on Logic-in-Memory (LiM) solutions, i.e., digital operations to accelerate Boolean Logic. In this context, we will provide a brief introduction on existing solutions based on memristive devices, together with benefits and limitations of such implementations.
The power and memory bottlenecks faced by today’s Von Neumann-based Neural Networks motivates the research on Neuromorphic Computing systems. The ambition of Neuromorphic chips is to get closer to bioinspired and even brain-inspired neuron and synapse computation models. Spiking Neural Networks (SNN) are an important class of bio-inspired computing paradigms offering promising solutions for on-chip cognitive applications. This talk will focus on the hardware-implemented Spiking Neural Networks with unsupervised, on-line learning. We will discuss the benefits and shortcomings of such neuromorphic systems, the possibilities of their hardware integration, and we will underline the main concerns related to their resilience face to different types of faults. An overview of pertinent fault models and a methodology for conducting fault injection campaigns is described and different scenarios of faulty behaviors occurring after/before the STDP learning will be discussed.
There is great interest in employing Convolutional Neural Networks (CNNs) in a variety of application fields presenting safety- and mission-critical requirements. In these scenarios it is crucial to assess the reliability of the computing system (composed of the CNN application running on top of a processing platform), to adopt (if necessary) specific hardening techniques. A number of existing approaches adopt the classical architecture-level fault injection to evaluate the vulnerability of a given CNN against faults. On the other hand, based on the idea that the sooner such analysis comes, the simpler and cheaper the design adjustments, other works adopt an application-level functional error simulation strategy. Moreover, some approaches only focus on the corruption of the CNN-specific parameters while other works extend the analysis to all applications variables/data memory locations. Finally, approaches adopt different strategies for classifying the corrupted outcome of the CNN, spanning from the classical bit-wise comparison to a usability-based analysis. In this talk we will review the most recent contributions related to the evaluation of the reliability of CNNs. Furthermore, we will present our attept to integrate the advatages of architecture-level fault injection and application-level error simulation into a unique analysis framework.