25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems – DDECS 2022

April 6 – 8, 2022
Prague | Czech Republic

Industrial Talks

Pavel Benáček, Intel
Experiences building a P4 Compiler for FPGAs


This talk introduces the emerging P4 ecosystem and describes novel research in targeting FPGAs with the P4 language. P4 is a hardware-agnostic, domain-specific language for network devices, specifying how the data plane should process packets. It is a new and developing standard that is gaining adoption across academia and industry, with P4 compiler toolchains targeting a wide range of commercial network hardware. Effectively mapping a P4 program to a given hardware or software target presents a complex optimization problem and is an active area of research. This programmability enables the user of a network device to customize its behavior for their use case. This innate flexibility is an ideal match for Field-Programmable Gate Arrays (FPGAs), which offer high-performance, inherently customizable programmable logic. A P4 compiler that can target FPGAs has the potential to expand the accessibility of this predominantly hardware-oriented technology to a wide range of non-RTL experts.

Pavel Benáček

Pavel Benáček received his Ph.D. in computer science at the Czech Technical University in Prague, Faculty of Information Technology for an automatic translation of P4 language into the RTL description of network device. Pavel’s interest is Hardware/Software Co-Design of high-speed network devices and parallel processing.

He was working as a researcher at CESNET with focus on hardware acceleration in the area of computer networks using FPGAs. Pavel is currently working as a compiler and SoC Engineer in Intel PSG group.

Safety-critical embedded software technology innovations in Sysgo


The talk briefly summarizes the outcomes and challenges in research and technology innovation in these areas:

  • Fuzz testing. PikeOS kernel is under very thorough and systematic testing and verification adequate to highest norms for developing safety-critical software. As fuzz testing is not required by these norms the approach has been adopted optionally. We briefly describe how it was adopted and what value it added in the context of already established verification processes.
  • Hardware-assisted host intrusion detection system evaluating code control-flow traces on platforms used for safety-critical applications.
  • Pioneering work on security certification of multiple independent levels of security (MILS) systems while composing Common Criteria certified subcomponent in the scope of IEC 62443-4 certified industrial system.