In this talk we give an overview of the AI methods and techniques used in the field of hardware security and side-channel analysis in particular. We first discuss the ways in which Machine learning and AI changed the side-channel analysis landscape and attackers’ capabilities in particular. We survey several examples of AI assisting with leakage evaluation and discuss the impact of it. Finally, we also consider the way side-channel analysis threatens AI implementations e.g. commonly used neural nets architectures.
Lejla Batina received her Ph.D. from KU Leuven, Belgium (2005) and also studied at the Eindhoven University of Technology, (Professional Doctorate in Engineering in 2001) and worked as a cryptographer for SafeNet B.V. (2001–2003). She is a professor in embedded systems security at the Radboud University in Nijmegen, the Netherlands.
She has authored or coauthored more than 100 refereed articles. Her current research interests include implementations of cryptography and hardware security. Her research group at Radboud consists of 12 researchers and 9 Ph.D. students have graduated under her supervision.
Dr. Batina a senior member of IEEE and an Editorial board member of top journals in security, such as IEEE Transactions on Information Forensics and Security and ACM Transactions on Embedded Computing Systems. She was program co-chair of CHES 2014, ACM WiSec 2021 and currently she serves a track chair of DATE 2022 (Track D: Design Methods and Tools).
With the growing demand for highly area-efficient, delay-optimized, and low-power designs, the complexity of digital circuits is increasing as well. Especially, a wide variety of arithmetic circuits, including different types of adders, multipliers, and dividers have been proposed to meet the demands in applications such as cryptography and Artificial Intelligence (AI). Some of these arithmetic circuits have highly parallel architectures and contain millions of gates; as a result, they are extremely error-prone. In the last 30 years, several formal verification methods have been proposed to verify arithmetic circuits. These methods report very good results when it comes to the verification of adders and structurally simple multipliers. Moreover, it is even possible to prove that the space and time complexities are polynomial in these cases. However, formal verification of structurally complex circuits is a big challenge since it requires heuristics that do not always work reliably.
We investigate the space and time complexity of verifying a structurally complex multiplier using a word-level verification method. We prove that the lower-bound complexities are always exponential for this multiplier. Then, we introduce a new verification strategy that takes advantage of using several verification engines. We show that the polynomial formal verification of the complex multiplier becomes possible if the correctness of each stage is verified separately using the proper verification method. Our verification strategy can also be applied to other complex digital circuits.
Rolf Drechsler received the Diploma and Dr. phil. nat. degrees in computer science from the Johann Wolfgang Goethe University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He worked at the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and at the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, Rolf Drechsler is Full Professor and Head of the Group of Computer Architecture, Institute of Computer Science, at the University of Bremen, Germany. In 2011, he additionally became the Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. From 2008 to 2013 he was the Vice Rector for Research and Young Academics at the University of Bremen. Since 2018 he is the Dean of the Faculty of Mathematics and Computer Science. He is a co-founder of the Graduate School of Embedded Systems and he is the coordinator of the Graduate School "System Design" funded within the German Excellence Initiative. He is a co-founder and the spokesperson of the Data Science Center at the University of Bremen.
Rolf Drechslers' current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. Rolf Drechsler is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, IET Cyber-Physical Systems: Theory & Applications, International Journal on Multiple-Valued Logic and Soft Computing, and ACM Journal on Emerging Technologies in Computing Systems.
Rolf Drechsler was a member of Program Committees of numerous conferences including e.g., DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, and FMCAD. He was Symposiums Chair at ISMVL 1999 and 2014, and the Topic Chair for "Formal Verification" at DATE 2004, DATE 2005, DAC 2010, and DAC 2011 and 2018. He was the General Chair of the IEEE European Test Symposium 2018 and the Program Chair of ICCAD 2020. He received best paper awards at the Haifa Verification Conference (HVC) in 2006, the Forum on specification & Design Languages (FDL) in 2007, 2010 and 2020, the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in 2010, the Euromirco Digital System Design Conference 2020 and the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2013 and 2018. He received the Berninghausen Award for Excellence in Teaching in 2018. Dr. Drechsler is IEEE Fellow.
A growing number of mission-critical and compute-intensive applications require extreme reliability through the entire lifecycle of the silicon. In autonomous vehicles, large scale data centers, cloud computing, and industrial electronics, we rely on DFT not only during manufacturing but through the entire silicon lifecycle which can span 10 years. For example, functional safety requirements for automotive electronics are addressed by Built-In Self-Test which periodically performs in-system testing.
To meet the performance demands, a more advanced technology nodes are adopted at an accelerated rate. The new technologies, especially at 7 nm and below, come with new more complex defects and reliability risks related to transistor aging and electromigration. It was recently observed in large scale data centers that aging related defects cause silent data corruption. Software tests are periodically run to identify cores effected by these failures. It is an expensive and not the most effective solution.
In chip manufacturing we primarily rely on deterministic structural tests to achieve high quality and only use functional tests as a supplement. In this talk we review how deterministic structural tests can also be applied during in-system to achieve high reliability. We discuss how to: meet the quality requirements, satisfy the constraints of in-system test (test time, memory, power), deliver the tests, and deal with arbitrary defect sensitivities discovered over time.
Janusz Rajski received the M.S. degree in electrical engineering from the Technical University of Gdańsk, Gdańsk, Poland, in 1973, and the Ph.D. degree in electrical engineering from the Poznań University of Technology, Poznań, Poland, in 1982.,From 1973 to 1984, he was a Faculty Member with the Poznań University of Technology. From 1984 to 1995, he was with McGill University, Montreal, QC, Canada. In January 1995, he accepted the position of Chief Scientist at Mentor Graphics, Wilsonville, OR, USA. He is currently a Vice President of Engineering at Siemens Digital Industries Software, Wilsonville, OR, USA.
He has authored more than 200 research papers in these areas and is a co-inventor of 125 U.S. patents. His papers and patents have over 14,000 citations and won many prestigious awards. He is also the Principal Inventor of the Embedded Deterministic Test technology used in the first commercial test compression product TestKompress. His main research interests include testing of VLSI systems, design for testability, built-in self-test, and logic synthesis.
Dr. Rajski was the co-recipient of the 1993 Best Paper Award for the article on logic synthesis published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the co-recipient of the 1995, 1998, and 2020 Best Paper Awards at the IEEE VLSI Test Symposium, the co-recipient of the 1999 and 2003 Honorable Mention Awards at the IEEE International Test Conference, as well as co-recipient of the 2006 IEEE Circuits and Systems Society Donald O. Pederson Outstanding Paper Award recognizing the article on embedded deterministic test published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the 2009 Best Paper Award at the VLSI Design Conference, the 2011 Best Paper Award at the IEEE European Test Symposium, and the 2012 IEEE International Test Conference Most Significant Paper Award. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor's DFT business to its current position as #1 test business in EDA”. In 2018, he received a Siemens Lifetime Achievement Award in recognition of his work in testing integrated circuits. He has served for program committees of various conferences. Dr. Rajski is Life Fellow of IEEE.